1. Field of the Invention
The present invention relates to a display device, and more particularly, to a driver for a display device.
2. Description of the Related Art
There is a demand for a flat panel display device having excellent characteristics, such as slim profile, lightweight and low power consumption. Such a flat panel display device includes a liquid crystal display (LCD), an organic light-emitting diode (OLED), a plasma display panel (PDP), and so on. Among them, the LCD or OLED is driven in an active matrix method.
An LCD will now be described. All of the following descriptions can also be applied to the OLED.
FIG. 1 is a block diagram of a related art LCD.
Referring to FIG. 1, the related art LCD includes a timing controller 100, a gate driver 103, a data driver 105, and a liquid crystal panel 107. The timing controller 100 generates a timing control signal using external vertical/horizontal synchronization signals (Vsync, Hsync), and the gate driver 103 sequentially supplies a scan signal in response to the timing control signal. The data driver 105 converts digital image data into analog image data (gray scale) in response to the timing control signal. The liquid crystal panel 107 displays an image corresponding to the analog image data to a pixel connected to a line (that is, a gate line) selected by the scan signal. The timing controller 100 supplies the external digital image data to the data driver 105.
Texas Instrument's mini Low Voltage Differential Signal (LVDS) can be used to provide the digital image data from the timing controller 100 to the data driver 105.
The LVDS is a standard interface between the timing controller 100 and the data driver 105.
FIG. 2 is a block diagram of a mini LVDS interface between the timing controller and the data driver in the LCD of FIG. 1.
Referring to FIG. 2, first and second data drivers 105a and 105b are connected through an RLV bus line 111 to the left of a timing controller 100, and third and fourth data drivers 105c and 105d are connected through an LLV bus line 113 to the right of the timing controller 100. For convenience of explanation and without limitation, a total of four data drivers are shown in FIG. 2, two on the right of the timing controller 100 and two on the left of the timing controller 100. In a large-sized panel display device, a larger number of data drivers may be provided on the right and/or left of the timing controller. Each of the data drivers 105a, 105b, 105c and 105d shifts 6-bit digital image data 64 times to output analog image data over 384 channels.
The timing controller 100 supplies the digital image data to the RLV bus line 111 and the LLV bus line 113. Also, the timing controller 100 supplies data reset signal through the RLV bus line 111 to the first data driver 105a and through the LLV bus line 113 to the third data driver 105c. Each of the first and third data drivers 105a and 105c converts the digital image data into analog image data in response to the data reset signal. The first data driver 105a converts the digital image data into the analog image data in response to the data reset signal. When the first data driver 105a completes the operation of converting the digital image data into the analog image data, a predetermined carry signal is inputted to the second data driver 105b. The second data driver 105b converts the digital image data into analog image data in response to the carry signal. The third data driver 105c converts the digital image data into the analog image data in response to the data reset data. When the third data driver 105c completes the operation of converting the digital image data into the analog image data, a predetermined carry signal is inputted to the fourth data driver 105d. The fourth data driver 105d converts the digital image data into analog image data in response to the carry signal.
Each of the first to fourth data drivers 105a, 105b, 105c and 105d includes a shift register (not shown), a first latch (not shown), a second latch (not shown), and a second latch (not shown), a digital-to-analog converter (DAC) (not shown), and an output buffer (not shown). The shift register sequentially outputs a sampling signal in response to the data reset signal or the carry signal. The first latch sequentially outputs the digital image data according to the sampling signal outputted from the shift register. The second latch simultaneously outputs the digital image data stored in the first latch. The DAC converts the digital image data into analog image data on which gamma voltage is reflected. The output buffer temporarily stores the analog image data outputted from the DAC and then outputs it.
In such a mini LVDS interface, the same number of data drivers is disposed on the left and right of the timing controller. Accordingly, an even number of the data drivers can be provided.
Alternatively, an odd number of data drivers may be provided in a large-sized panel display device. An additional data driver may be provided to the left or right of the timing controller. When the data drivers to the left and right of the timing controller are driven simultaneously, the side that has the additional data driver will have a longer driving time. Since the driving time is different in the two sides of the timing controller an equal driving frequency cannot be used. Consequently, different driving frequencies must be used in the data drivers disposed on both sides of the timing controller.
When the number of the data drivers is different on both sides of the timing controller, the interface between the timing controller and the data driver in the LCD may be redesigned to provide for an even number of the data drivers. However, changing the design of the interface expends a large amount of time and the existing data drivers cannot be used, thereby resulting in a waste of resources.